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cy8c29466 automotive psoc ? programmable system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-12899 rev. *b revised september 25, 2009 features aec qualified powerful harvard architecture processor ? m8c processor speeds up to 24 mhz ? two 8x8 multiply, 32-bit accumulate ? low power at high speed ? 3.0v to 5.25v operating voltage ? automotive temperature range: -40c to +85c advanced peripherals (psoc ? blocks) ? 12 rail-to-rail analog psoc blocks provide: ? up to 14-bit adcs ? up to 9-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? 16 digital psoc blocks provide: ? 8- to 32-bit timers, counters, and pwms ? crc and prs modules ? up to four full-duplex or eight half-duplex uarts ? multiple spi masters or slaves ? connectable to all gpio pins ? complex peripherals by combining blocks precision, programmable clocking ? internal 5% 24/48 mhz oscillator ? high accuracy 24 mhz with optional 32.768 khz crystal and pll ? optional external oscillator, up to 24 mhz ? internal low speed, low power oscillator for watchdog and sleep functionality flexible on-chip memory ? 32k bytes flash program storage, 1000 erase/write cycles ? 2k bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink, 10 ma drive on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 12 analog inputs on gpio [1] ? four 30 ma analog outputs on gpio ? configurable interrupt on all gpio additional system resources ? i 2 c master, slave, or multi-master operation up to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full featured in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k bytes trace memory ? complex events ? c compilers, assembler, and linker logic block diagram digital system sram 2k interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 32k digital block array two multiply accums. internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog block array analog ref. analog input muxing i c 2 port 5 port 4 port 3 port 2 port 1 port 0 analog drivers system bus note 1. there are eight standard analog inputs on the gpio. the other four analog inputs connect from the gpio directly to specific s witched-capacitor block inputs. see the psoc technical reference manual for more details [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 2 of 34 psoc functional overview the psoc programmable system-on-chip family consists of many devices with on-chip controllers. these devices are designed to replace multiple traditional mcu-based system components with one, low cost single-chip programmable device. psoc devices include configurable blocks of analog and digital logic, as well as programmable interconnects. this archi- tecture enables the user to crea te customized peripheral config- urations that match the require ments of each individual appli- cation. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the psoc architecture, as illustrated in the logic block diagram on page 1, is comprised of four main areas: psoc core, digital system, analog system, and syst em resources. configurable global buses allow all the device resources to be combined into a complete custom system. th e automotive psoc cy8c29x66 family can have up to three i/o ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks. the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpio (general purpose io). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8- bit harvard architecture micro- processor. the cpu utilizes an interrupt controller with 25 vectors, to simplify programmi ng of real time embedded events. program execution is timed an d protected using the included sleep timer and watch dog timer (wdt). memory includes 32k of flash for program storage and 2k of sram for data storage. program flash utilizes four protection levels on blocks of 64 bytes, allowing customized software ip protection. the psoc device incorporates flexible internal clock generators, including a 24 mhz imo (internal main oscillator) accurate to 5% over temperature and voltage. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. if crystal accuracy is desired, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24 mhz system clock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital resources, and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfacing. every pin also has the capability to generate a system interrupt. the digital system the digital system is composed of 16 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user modules. digital pe ripheral configurations include those listed here. pwms (8 to 32 bit) pwms with dead band (8 to 24 bit) counters (8 to 32 bit) timers (8 to 32 bit) full or half-duplex 8-bit uart with selectable parity (up to 4 full-duplex or 8 half-duplex) spi master and slave (up to 8 total) i 2 c master, slave, or multi-master cyclical redundancy checker/generator (16 bit) irda (up to 4) pseudo random sequence generators (8 to 32 bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by psoc device fa mily. this allows the optimum choice of system resources fo r your application. family resources are shown in ta b l e 1 on page 4. figure 1. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 1 dbb10 dbb11 dcb12 dcb13 row input configuration 4 4 row output configuration row input configuration row output configuration row 2 dbb20 dbb21 dcb22 dcb23 4 4 row 0 dbb00 dbb01 dcb02 dcb03 4 4 row input configuration row output configuration row 3 dbb30 dbb31 dcb32 dcb33 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 5 port 4 port 3 port 2 port 1 port 0 [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 3 of 34 the analog system the analog system is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support spec ific application requirements. some of the common psoc analog functions for this device (most available as user modules) are as follows: analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as incremental, delta-sigma, and sar) filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch) amplifiers (up to 4, with selectable gain up to 48x) instrumentation amplifiers (up to 2, with selectable gain up to 93x) comparators (up to 4, with 16 selectable thresholds) dacs (up to 4, with 6- to 9-bit resolution) multiplying dacs (up to 4, with 6- to 9-bit resolution) high current output drivers (four with 30 ma drive as a psoc core resource) 1.3v reference (as a system resource) dtmf dialer correlators peak detectors many other topologies possible analog blocks are provided in co lumns of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks, as shown in figure 2 . figure 2. analog system block diagram acb00 acb01 block array array input configuration aci1[1:0] aci2[1:0] acb02 acb03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 4 of 34 additional system resources system resources, some of which have been previously listed, provide additional capability useful for complete systems. additional resources include a multiplier, decimator, low voltage detection, and power on reset. brief statements describing the merits of each system resource are given below: digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using di gital psoc blocks as clock dividers. two multiply accumulates (macs) provide fast 8-bit multiplier with 32-bit accumulate to assist in both general math as well as digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma adcs. the i 2 c module provides 0 to 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates t he need for a system supervisor. an internal 1.3v voltage reference provides an absolute reference for the analog system, including adcs and dacs. psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have a varying number of digital and analog blocks. the following table list s the resources available for specific psoc device groups. the psoc device covered by this data sheet is highlighted in ta b l e 1 . getting started the quickest way to understand psoc silicon is to read this data sheet and then use the psoc designer integrated development environment (ide). this data sh eet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the psoc ? technical reference manual for cy8c29x66 psoc devices. for up-to-date ordering, packaging, and electrical specification information, see the latest pso c device data sheets on the web at www.cypress.com/psoc . application notes application notes are an excellent introduction to the wide variety of possible psoc designs. they are located here: www.cypress.com/psoc . select application notes under the documentation tab. development kits psoc development kits are available online from cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical traini ng (on demand, webinars, and workshops) is available online at www.cypress.com/training . the training covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to www.cypress.com/cypros . solutions library visit our growing library of solution focused designs at www.cypress.com/solutions . here you can fi nd various appli- cation designs that include firmware and hardware design files that enable you to comple te your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at www.cypress.com/support . if you cannot find an answer to your question, call technical support at 1-800-541-4736. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 [2] up to 64 4 16 12 4 4 12 2k 32k cy8c27x43 up to 44 2 8 12 4 4 12 256 bytes 16k cy8c24x94 64 1 4 48 2 2 6 1k 16k cy8c24x23a [2] up to 24 1412226256 bytes 4k cy8c23x33 up to 1 4 12 2 2 4 256 bytes 8k cy8c21x34 [2] up to 28 1 4 28 0 2 4 [3] 512 bytes 8k cy8c21x23 16 1 4 8 0 2 4 [3] 256 bytes 4k cy8c20x34 up to 28 0 0 28 0 0 3 [3,4] 512 bytes 8k notes 2. automotive qualified devices available in this group. 3. limited analog functionality . 4. two analog blocks and one capsense. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 5 of 34 development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide runs on windows xp or windows vista. this system provides design database management by project, an integrated debugger with in -circuit emulator, in-system programming support, and built -in support for third-party assemblers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the psoc family. psoc designer software subsystems system-level view a drag-and-drop visual embedded system design environment based on psoc express. in the system level view you create a model of your system inputs, ou tputs, and comm unication inter- faces. you define when and how an output device changes state based upon any or all other syst em devices. based upon the design, psoc designer automatically selects one or more psoc mixed-signal controllers that match your system requirements. psoc designer generates all embedded code, then compiles and links it into a programming file for a specific psoc device. chip-level view the chip-level view is a more traditional integrated development environment (ide) based on psoc designer 4.4. choose a base device to work with and then select different onboard analog and digital components called user modules that use the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. configure the us er modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic configuration allows for changing configurations at run time. hybrid designs you can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. all views of the project share a common code editor, builder, and common deb ug, emulation, and programming tools. code generation tools psoc designer supports multiple third party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow a ssembly code to merge seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an inter nal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write i/o registers, read and write cpu registers, set and clear breakpoints, and provide program run, halt, and st ep control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials an d links to faqs and an online support forum to aid the designer in getting started. in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to progra m single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 6 of 34 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process can be summarized in the following four steps: 1. select components 2. configure components 3. organize and connect 4. generate, verify, and debug select components both the system-level and chip-l evel views provide a library of prebuilt, pretested hardware peripheral components. in the system-level view, these com ponents are called ?drivers? and correspond to inputs (a thermistor, for example), outputs (a brushless dc fan, for example), communication interfaces (i 2 c-bus, for example), and the logic to control how they interact with one another (called valuators). in the chip-level view, the components are called ?user modules?. user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. configure components each of the components you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the pa rameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. both the system-level drivers an d chip-level user modules are documented in data sheets that are viewed directly in the psoc designer. these data sheets explain the internal operation of the component and provide performance specifications. each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. organize and connect you can build signal chains at the chip level by interconnecting user modules to each other and the i/o pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. in the system-level view, sele cting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (pga) to buffer the input from the potentiometer, an analog to digital converter (adc) to conver t the potentiometer?s output to a digital signal, and a pwm to control the fan. in the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the software for the system. both system-level and chip-lev el designs generate software based on your design. the chip-level design provides application programming interfaces (apis) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. the system-level design also generates a c ma in() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in -circuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 7 of 34 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 7 on page 12 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or ?0x? are decimal. table 2. acronyms acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator i/o input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc programmable system-on-chip pwm pulse width modulator sc switched capacitor sram static random access memory [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 8 of 34 pinouts the automotive cy8c29x66 psoc devi ce is available in a variety of packages which are listed and illustrated in the following ta bles. every port pin (labeled with a ?p?) is capable of digital i/o. however, vss, vdd, and xres are not capable of digital i/o. 28-pin part pinout table 3. 28-pin part pinout (ssop) pin no. type pin name description figure 3. cy8c29466 28-pin psoc device digital analog 1 i/o i p0[7] analog column mux input. 2 i/o i/o p0[5] analog column mux input and column output. 3 i/o i/o p0[3] analog column mux input and column output. 4 i/o i p0[1] analog column mux input. 5 i/o p2[7] 6 i/o p2[5] 7 i/o i p2[3] direct switched capacitor block input. 8 i/o i p2[1] direct switched capacitor block input. 9 power vss ground connection. 10 i/o p1[7] i 2 c serial clock (scl). 11 i/o p1[5] i 2 c serial data (sda). 12 i/o p1[3] 13 i/o p1[1] crystal input (xtalin), i 2 c serial clock (scl), issp-sclk [5] . 14 power vss ground connection. 15 i/o p1[0] crystal output (xtalout), i 2 c serial data (sda), issp-sdata [5] . 16 i/o p1[2] 17 i/o p1[4] optional external clock input (extclk). 18 i/o p1[6] 19 input xres active high external reset with internal pull down. 20 i/o i p2[0] direct switched capacitor block input. 21 i/o i p2[2] direct switched capacitor block input. 22 i/o p2[4] external analog ground (agnd). 23 i/o p2[6] external voltage reference (vref). 24 i/o i p0[0] analog column mux input. 25 i/o i/o p0[2] analog column mux input and column output. 26 i/o i/o p0[4] analog column mux input and column output. 27 i/o i p0[6] analog column mux input. 28 power vdd supply voltage. legend : a = analog, i = input, and o = output. ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] p2[7] p2[5] ai, p2[3] ai, p2[1] vss i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss vdd p0[6], ai p0[4], aio p0[2], aio p0[0], ai p2[6], external vref p2[4], external agnd p2[2], ai p2[0], ai xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sda note 5. these are the issp pins, which are not high z when coming out of por (power on reset). see the psoc technical reference manual for details. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 9 of 34 registers register conventions this section lists the the regist ers of the automo tive cy8c29x66 psoc device. for detailed register information, reference the psoc technical reference manual. the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks. the xio bit in the flag register (cpu_f) determines which bank the user is currently in. when the xio bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. table 4. abbreviations convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 10 of 34 table 5. register map bank 0 table: user space name addr (0, hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbb20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbb20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbb20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbb20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbb21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbb21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbb21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbb21cr0 47 # asd11cr3 87 rw c7 prt2dr 08 rw dcb22dr0 48 # asc12cr0 88 rw rdi3ri c8 rw prt2ie 09 rw dcb22dr1 49 w asc12cr1 89 rw rdi3syn c9 rw prt2gs 0a rw dcb22dr2 4a rw asc12cr2 8a rw rdi3is ca rw prt2dm2 0b rw dcb22cr0 4b # asc12cr3 8b rw rdi3lt0 cb rw prt3dr 0c rw dcb23dr0 4c # asd13cr0 8c rw rdi3lt1 cc rw prt3ie 0d rw dcb23dr1 4d w asd13cr1 8d rw rdi3ro0 cd rw prt3gs 0e rw dcb23dr2 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3dm2 0f rw dcb23cr0 4f # asd13cr3 8f rw cf prt4dr 10 rw dbb30dr0 50 # asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw dbb30dr1 51 w asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw dbb30dr2 52 rw asd20cr2 92 rw d2 prt4dm2 13 rw dbb30cr0 53 # asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw dbb31dr0 54 # asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw dbb31dr1 55 w asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw dbb31dr2 56 rw asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw dbb31cr0 57 # asc21cr3 97 rw i2c_scr d7 # 18 dcb32dr0 58 # asd22cr0 98 rw i2c_dr d8 rw 19 dcb32dr1 59 w asd22cr1 99 rw i2c_mscr d9 # 1a dcb32dr2 5a rw asd22cr2 9a rw int_clr0 da rw 1b dcb32cr0 5b # asd22cr3 9b rw int_clr1 db rw 1c dcb33dr0 5c # asc23cr0 9c rw int_clr2 dc rw 1d dcb33dr1 5d w asc23cr1 9d rw int_clr3 dd rw 1e dcb33dr2 5e rw asc23cr2 9e rw int_msk3 de rw 1f dcb33cr0 5f # asc23cr3 9f rw int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbb10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbb10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbb10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbb10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbb11cr0 37 # acb01cr2 77 rw b7 cpu_f f7 rl dcb12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcb12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcb12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcb12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcb13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw fc dcb13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw fd dcb13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcb13cr0 3f # acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 11 of 34 table 6. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbb20fn 40 rw asc10cr0 80 rw rdi2ri c0 rw prt0dm1 01 rw dbb20in 41 rw asc10cr1 81 rw rdi2syn c1 rw prt0ic0 02 rw dbb20ou 42 rw asc10cr2 82 rw rdi2is c2 rw prt0ic1 03 rw 43 asc10cr3 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbb21fn 44 rw asd11cr0 84 rw rdi2lt1 c4 rw prt1dm1 05 rw dbb21in 45 rw asd11cr1 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbb21ou 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw dcb22fn 48 rw asc12cr0 88 rw rdi3ri c8 rw prt2dm1 09 rw dcb22in 49 rw asc12cr1 89 rw rdi3syn c9 rw prt2ic0 0a rw dcb22ou 4a rw asc12cr2 8a rw rdi3is ca rw prt2ic1 0b rw 4b asc12cr3 8b rw rdi3lt0 cb rw prt3dm0 0c rw dcb23fn 4c rw asd13cr0 8c rw rdi3lt1 cc rw prt3dm1 0d rw dcb23in 4d rw asd13cr1 8d rw rdi3ro0 cd rw prt3ic0 0e rw dcb23ou 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3ic1 0f rw 4f asd13cr3 8f rw cf prt4dm0 10 rw dbb30fn 50 rw asd20cr0 90 rw gdi_o_in d0 rw prt4dm1 11 rw dbb30in 51 rw asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw dbb30ou 52 rw asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw dbb31fn 54 rw asc21cr0 94 rw d4 prt5dm1 15 rw dbb31in 55 rw asc21cr1 95 rw d5 prt5ic0 16 rw dbb31ou 56 rw asc21cr2 96 rw d6 prt5ic1 17 rw 57 asc21cr3 97 rw d7 18 dcb32fn 58 rw asd22cr0 98 rw d8 19 dcb32in 59 rw asd22cr1 99 rw d9 1a dcb32ou 5a rw asd22cr2 9a rw da 1b 5b asd22cr3 9b rw db 1c dcb33fn 5c rw asc23cr0 9c rw dc 1d dcb33in 5d rw asc23cr1 9d rw osc_go_en dd rw 1e dcb33ou 5e rw asc23cr2 9e rw osc_cr4 de rw 1f 5f asc23cr3 9f rw osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 w dcb02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef dbb10fn 30 rw acb00cr3 70 rw rdi0ri b0 rw f0 dbb10in 31 rw acb00cr0 71 rw rdi0syn b1 rw f1 dbb10ou 32 rw acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11fn 34 rw acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11in 35 rw acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11ou 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl dcb12fn 38 rw acb02cr3 78 rw rdi1ri b8 rw f8 dcb12in 39 rw acb02cr0 79 rw rdi1syn b9 rw f9 dcb12ou 3a rw acb02cr1 7a rw rdi1is ba rw fls_pr1 fa rw 3b acb02cr2 7b rw rdi1lt0 bb rw fb dcb13fn 3c rw acb03cr3 7c rw rdi1lt1 bc rw fc dcb13in 3d rw acb03cr0 7d rw rdi1ro0 bd rw fd dcb13ou 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # 3f acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 12 of 34 electrical specifications this section presents the dc and ac electr ical specifications of the cy8c29x66 psoc device. for the most up to date electrical specifications, confirm that you have th e most recent data sheet by visiting http://www.cypress.com/psoc. specifications are valid for -40c t a 85c and t j 100c, except where noted. refer to table 20 on page 21 for the electrical specific ations of the internal main oscilla tor (imo) using slow imo (slimo) mode. figure 4. voltage versus cpu frequency figure 5. imo frequency trim options the following table lists the units of me asure that are used in this section. 5.25 4.75 93 khz 24 mhz cpu frequency (nominal setting) vdd voltage (v) 0 12 mhz 3.0 v a l i d o p e r a t i n g r e g i o n slimo mode=0 slimo mode=0 slimo mode=1 5.25 4.75 6 mhz 24 mhz imo frequency vdd voltage (v) 0 12 mhz 3.0 3.6 slimo mode=1 table 7. units of measure symbol unit of measure symbol unit of measure c degree celsius vrms microvolts root-mean-square db decibels w microwatts ff femto farad ma milli-ampere hz hertz ms milli-second kb 1024 bytes mv milli-volts kbit 1024 bits na nanoampere khz kilohertz ns nanosecond k kilohm nv nanovolts mbaud megabaud ohm mbps megabits per second pa picoampere mhz megahertz pf picofarad m megaohm pp peak-to-peak a microampere ppm parts per million f microfarad ps picosecond h microhenry sps samples per second s microsecond sigma: one standard deviation v microvolts v volts [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 13 of 34 absolute maximum ratings operating temperature symbol description min typ max units notes t stg storage temperature -55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25c 25c. extended duration storage temperatures above 65c degrades reliability. t a ambient temperature with power applied -40 ? +85 c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tristate vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma i maio maximum current into an y port pin configured as analog driver -50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma symbol description min typ max units notes t a ambient temperature -40 ? +85 c t j junction temperature -40 ? +100 c the temperature rise from ambient to junction is package specific. see thermal impedances on page 30. the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 14 of 34 dc electrical characteristics dc chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. dc general purpose i/o specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 8. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v see dc por and lvd specifications on page 19. i dd supply current ? 8 14 ma conditions are 5.25v, cpu = 3 mhz, 48 mhz disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i dd3 supply current ? 5 9 ma conditions are vdd = 3.3v, cpu = 3 mhz, 48 mhz disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i ddp supply current when imo = 6 mhz using slimo mode. ? 2 3 ma conditions are vdd = 3.3v, cpu = 3 mhz, 48 mhz disabled, vc1 = 0.375 mhz, vc2 = 23.44 khz, vc3 = 0.09 khz. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal low speed oscil- lator active. ? 4 25 a conditions are with internal low speed oscillator, vdd = 3.3v, -40c t a 85c. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, internal low speed oscillator, and 32 khz crystal oscillator active. ? 4 27 a conditions c are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, -40c t a 85c. v ref reference voltage (bandgap) 1.28 1.3 1.32 v trimmed for appropriate vdd. table 9. dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v i oh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5] )). 80 ma maximum combined i oh budget. v ol low output level ? ? 0.75 v i ol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined i ol budget. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.1 ? v vdd = 3.0 to 5.25. v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25c. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 15 of 34 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog continuous time (ct) psoc blocks and the analog switched capacitor (sc) psoc blocks. the guar anteed specifications are measured in the analog continuous time psoc block. typical parameters apply to 5v at 25 c and are for design guidance only. table 10. 5v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.6 1.3 1.2 10 8 7.5 mv mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25c. v cmoa common mode voltage range. all cases, except highest. power = high, opamp bias = high 0.0 0.5 ? ? vdd vdd - 0.5 v v cmrr oa common mode rejection ratio 60 ? ? db g oloa open loop gain 80 ? ? db v ohighoa high output voltage swing (internal signals) vdd - 0.01 ? ? v v olowoa low output voltage swing (internal signals) ? ? 0.01 v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 67 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd . table 11. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high high power is 5 volts only ? ? 1.65 1.32 10 8 mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c . v cmoa common mode voltage range 0 ? vdd v cmrr oa common mode rejection ratio 60 ? ? db g oloa open loop gain 80 ? ? db v ohighoa high output voltage swing (internal signals) vdd - 0.01 ? ? v v olowoa low output voltage swing (internal signals) ? ? 0.01 v [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 16 of 34 dc low power comparator specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c and are for design guidance only. i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 ? 200 400 800 1600 3200 ? a a a a a ? not allowed psrr oa supply voltage rejection ratio 54 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd table 11. 3.3v dc operational amplifier specifications (continued) symbol description min typ max units notes table 12. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 17 of 34 dc analog output bu ffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 13. 5v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 ? vdd - 1.0 v r outob output resistance power = low power = high ? ? ? ? 1 1 v ohighob high output voltage swing (load = 32 to vdd/2) power = low power = high 0.5 x vdd + 1.3 0.5 x vdd + 1.3 ? ? ? ? v v v olowob low output voltage swing (load = 32 to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.3 0.5 x vdd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 2 5 ma ma psrr ob supply voltage rejection ratio 40 64 ? db table 14. 3.3v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? ? ? 10 10 v ohighob high output voltage swing (load = 1 k to vdd/2) power = low power = high 0.5 x vdd + 1.0 0.5 x vdd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1 k to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.0 0.5 x vdd - 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? ? 0.8 2.0 1 5 ma ma psrr ob supply voltage rejection ratio 60 64 ? db [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 18 of 34 dc analog reference specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the guaranteed specificat ions are measured through the anal og continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power levels for refhi and reflo refer to the a nalog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. note avoid using p2[4] for digital signaling when using an analog resource that depends on the a nalog reference. some coupling of the digital signal may appear on the agnd. table 15. 5v dc analog reference specifications symbol description min typ max units v bg5 bandgap voltage reference 5v 1.28 1.30 1.32 v ? agnd = vdd/2 [6] vdd/2 - 0.02 vdd/2 vdd/2 + 0.02 v ? agnd = 2 x bandgap [6] 2.52 2.60 2.72 v ? agnd = p2[4] (p2[4] = vdd/2) [6] p2[4] - 0.013 p2[4] p2[4] + 0.013 v ? agnd = bandgap [6] 1.27 1.3 1.34 v ? agnd = 1.6 x bandgap [6] 2.03 2.08 2.13 v ? agnd block to block variation (agnd = vdd/2) [6] -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap [7] vdd/2 + 1.21 vdd/2 + 1.3 vdd/2 + 1.382 v ? refhi = 3 x bandgap [7] 3.75 3.9 4.05 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) [7] p2[6] + 2.478 p2[6] + 2.6 p2[6] + 2.722 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) [7] p2[4] + 1.218 p2[4] + 1.3 p2[4] + 1.382 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) [7] p2[4] + p2[6] - 0.058 p2[4] + p2[6] p2[4] + p2[6] + 0.058 v ? refhi = 2 x bandgap [7] 2.50 2.60 2.70 v ? refhi = 3.2 x bandgap [7] 4.02 4.16 4.29 v ? reflo = vdd/2 - bandgap [7] vdd/2 - 1.369 vdd/2 - 1.30 vdd/2 - 1.231 v ? reflo = bandgap [7] bg - 0.082 bg + 0.023 bg + 0.129 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) [7] 2 x bg - p2[6] - 0.084 2 x bg - p2[6] + 0.025 2 x bg - p2[6] + 0.134 v ? reflo = p2[4] - bandgap (p2[4] = vdd/2) [7] p2[4] - bg - 0.056 p2[4] - bg + 0.026 p2[4] - bg + 0.107 v ? reflo = p2[4] - p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) [7] p2[4] - p2[6] - 0.057 p2[4] - p2[6] + 0.026 p2[4] - p2[6] + 0.110 v table 16. 3.3v dc analog reference specifications symbol description min typ max units v bg33 bandgap voltage reference 3.3v 1.28 1.30 1.32 v ? agnd = vdd/2 [6] vdd/2 - 0.02 vdd/2 vdd/2 + 0.02 v ? agnd = 2 x bandgap [6] not allowed ? agnd = p2[4] (p 2[4] = vdd/2) [6] p2[4] - 0.009 p2[4] p2[4] + 0.009 v ? agnd = bandgap [6] 1.27 1.30 1.34 v ? agnd = 1.6 x bandgap [6] 2.03 2.08 2.13 v ? agnd block to block variation (agnd = vdd/2) [6] -0.034 0.000 0.034 mv ? refhi = vdd/2 + bandgap [7] not allowed ? refhi = 3 x bandgap [7] not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5v) [7] not allowed notes 6. this specification is only va lid when ct block power = high. agnd tolerance includes the offsets of the local buffer in the p soc block. 7. this specification is only valid when ref control power = high. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 19 of 34 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. dc por and lvd specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. ? refhi = p2[4] + bandg ap (p2[4] = vdd/2) [7] not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) [7] p2[4] + p2[6] - 0.042 p2[4] + p2[6] p2[4] + p2[6] + 0.042 v ? refhi = 2 x bandgap [7] 2.50 2.60 2.70 v ? refhi = 3.2 x bandgap [7] not allowed ? reflo = vdd/2 - bandgap [7] not allowed ? reflo = bandgap [7] not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) [7] not allowed ? reflo = p2[4] - bandgap (p2[4] = vdd/2) [7] not allowed ? reflo = p2[4] - p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) [7] p2[4] - p2[6] - 0.036 p2[4] - p2[6] p2[4] - p2[6] + 0.036 v table 16. 3.3v dc analog reference specifications(continued) symbol description min typ max units table 17. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k c sc capacitor unit value (switch cap) ? 80 ? ff table 18. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.82 4.39 4.55 ? ? ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 [8] 3.08 3.20 4.08 4.57 4.74 [9] 4.82 4.91 v v v v v v v v notes 8. always greater than 50 mv above ppor (porlev = 00) for falling supply. 9. always greater than 50 mv above ppor (porlev = 10) for falling supply. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 20 of 34 dc programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 19. dc programming specifications symbol description min typ max units notes i ddp supply current during programming or verify ? 10 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) [10] 1,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [11] 512,000 ? ? ? erase/write cycles. flash dr flash data retention 15 ? ? years notes 10. for the full temperature range, the user must employ a temper ature sensor user module (flashtemp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 11. a maximum of 512 x 100 block endurance cycles is allowed. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 21 of 34 ac electrical characteristics ac chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 20. ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 22.8 [12] 24 25.2 [12] mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 4 on page 12. slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.5 [12] 6 6.5 [12] mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 4 on page 12. slimo mode = 1. f cpu1 cpu frequency (5v nominal) 0.089 [12] 24 25.2 [12] mhz 4.75v vdd 5.25v f cpu2 cpu frequency (3.3v nominal) 0.089 [12] 12 12.6 [12] mhz 3.0v vdd 3.6v f 48m digital psoc block frequency 0 48 50.4 [12, 13] mhz refer to the table 25 on page 26. f 24m digital psoc block frequency 0 24 25.2 [12, 13] mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz trimmed. during power up ilo is untrimmed and minimum is 5khz. f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f pll pll frequency ? 23.986 ? mhz a multiple (x732) of crystal frequency. jitter24m2 24 mhz period jitter (pll) ? ? 600 ps t pllslew pll lock time 0.5 ? 10 ms refer to figure 6 on page 22 . t pllslewlow pll lock time for low gain setting 0.5 ? 50 ms refer to figure 7 on page 22 . t os external crystal oscillator startup to 1% ? 250 500 ms refer to figure 8 on page 22. t osacc external crystal oscillator startup to 100 ppm ? 300 600 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 w maximum drive level 32.768 khz crystal. 3.0v vdd 5.25v, -40c t a 85c. jitter32k 32 khz period jitter ? 100 ? ns refer to figure 10 on page 22 . t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 45.6 [12] 48.0 50.4 [12] mhz trimmed. using factory trim values. jitter24m1 24 mhz period jitter (imo) ? 600 ? ps refer to figure 9 on page 22 . f max maximum frequency of signal on row input or row output. ? ? 12.6 [12] mhz t ramp supply ramp time 20 ? ? s notes 12. accuracy derived from internal main oscillator (imo) with appropriate trim for vdd range. 13. see the individual user module data sheets for information on maximum frequencies for user modules. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 22 of 34 figure 6. pll lock timing diagram figure 7. pll lock for low gain setting timing diagram figure 8. external crystal oscillator startup timing diagram figure 9. 24 mhz period jitter (imo) timing diagram figure 10. 32 khz period jitter (eco) timing diagram 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1 32 khz f 32k2 32k select t os jitter24m1 f 24m jitter32k f 32k2 [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 23 of 34 ac general purpose i/o specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 11. gpio timing diagram table 21. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.6 [12] mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 24 of 34 ac operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3v. table 22. 5v ac operationa l amplifier specifications symbol description min typ max units notes t roa rising settling time to 0.1% for a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time to 0.1% for a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ s v/ s v/ s sr foa falling slew rate (80% to 20%) of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ s v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 23. 3.3v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time to 0.1% of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time to 0.1% of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ s v/ s sr foa falling slew rate (80% to 20%) of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 25 of 34 when bypassed by a capacitor on p2[4], the noise of the analog ground signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1 k resistance and the external capacitor. figure 12. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 13. typical opamp noise 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq ( khz ) dbv/rthz 0 0.01 0.1 1.0 10 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 26 of 34 ac low power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c and are for design guidance only. ac digital block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 24. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 25. ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency (vdd > 4.75v) ? ? 50.4 [12] mhz 4.75v vdd 5.25v. maximum block clocking frequency (vdd < 4.75v) ? ? 25.2 [12] mhz 3.0v vdd 4.75v. timer capture pulse width 50 [14] ? ? ns maximum frequency, no capture ? ? 50.4 [12] mhz 4.75v vdd 5.25v. maximum frequency, with capture ? ? 25.2 [12] mhz counter enable pulse width 50 [14] ? ? ns maximum frequency, no enable input ? ? 50.4 [12] mhz 4.75v vdd 5.25v. maximum frequency, enable input ? ? 25.2 [12] mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [14] ? ? ns disable mode 50 [14] ? ? ns maximum frequency ? ? 50.4 [12] mhz 4.75v vdd 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 50.4 [12] mhz 4.75v vdd 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 25.2 [12] mhz spim maximum input clock frequency ? ? 8.4 [12] mhz maximum data rate is 4.2 mbps due to 2 x over clocking. spis maximum input clock frequency ? ? 4.2 [12] mhz width of ss_ negated between transmissions 50 [14] ? ? ns trans- mitter maximum input clock frequency ? ? 25.2 [12] mhz maximum baud rate is 3.15 mbaud due to 8 x over clocking. maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? 50.4 [12] mhz maximum baud rate is 6.30 mbaud due to 8 x over clocking receiver maximum input clock frequency ? ? 25.2 [12] mhz maximum baud rate is 3.15 mbaud due to 8 x over clocking. maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? 50.4 [12] mhz maximum baud rate is 6.30 mbaud due to 8 x over clocking. note 14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 27 of 34 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 26. 5v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 4 4 s s t sob falling settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 3.4 3.4 s s sr rob rising slew rate (20% to 80%), 1v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100 pf load power = low power = high 0.55 0.55 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20 mv pp , 3 db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3 db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 27. 3.3v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 4.7 4.7 s s t sob falling settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 4 4 s s sr rob rising slew rate (20% to 80%), 1v step, 100 pf load power = low power = high 0.36 0.36 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100 pf load power = low power = high 0.4 0.4 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20 mv pp , 3 db bw, 100 pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3 db bw, 100 pf load power = low power = high 200 200 ? ? ? ? khz khz [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 28 of 34 ac external clock specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. ac programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 28. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 29. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle require- ments. f oscext frequency with cpu clock divide by 2 or greater 0.093 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider will ensure that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 30. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns vdd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 29 of 34 ac i 2 c specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 14. definition for timing for fast/standard mode on the i 2 c bus table 31. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 [15] 0400 [15] khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ?100 [16] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns notes 15. f scli2c is derived from sysclk of the psoc. this specification assumes that sysclk is oper ating at 24 mhz, nominal. if sysclk is at a lower frequency, then the f scli2c specification adjusts accordingly. 16. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudati2c 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 30 of 34 packaging information this section illustrates the packaging specifications for the automotive cy8c29x66 psoc device, along with the thermal impedanc es and solder reflow for each package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the drawings at http://www.cypress.com/design/mr10161 . figure 15. 28-pin (210-mil) ssop thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. 51-85079 *c table 32. thermal impedances per package package typical ja [17] 28 ssop 94c/w table 33. typical package capacitance on crystal pins package package capacitance 28 ssop 2.8 pf table 34. solder reflow peak temperature package minimum peak temperature [18] maximum peak temperature 28 ssop 240c 260c notes 17. t j = t a + power x ja 18. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5c with sn -pb or 245 5c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 31 of 34 development tool selection this section presents the development tools available for the cy8c29x66 family. software psoc designer at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for years. psoc designer is available free of charge at http://www.cypress.com. psoc designer comes with a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress. com/psocprogrammer. development kits all development kits can be purchased from the cypress online store. the online store ( www.cypress.com/shop ) also has the most up to date information on kit contents, descriptions, and availability. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the contents of specific memory locations. advanced emulation features are also supported through psoc designer. the kit includes: ice-cube unit 28-pin pdip emulation pod for cy8c29466-24pxi 28-pin cy8c29466-24pxi pdip psoc device samples (two) psoc designer software cd issp cable minieval socket programming and evaluation board backward compatibility cable (for connecting to legacy pods) universal 110/220 power supply (12v) european plug adapter usb 2.0 cable getting started guide development kit registration form evaluation tools all evaluation tools can be purchased from the cypress online store. the online store ( www.cypress.com/shop ) also has the most up to date information on kit contents, descriptions, and availability. cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, an rs-232 port, and plenty of breadboarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3210-29x66 evaluation pod (evalpod) psoc evalpods are pods that connect to the ice in-circuit emulator (cy3215-dk kit) to allow debugging capability. they can also function as a standalone device without debugging capability. the evalpod has a 28-pin dip footprint on the bottom for easy connection to development kits or other hardware. the top of the evalpod has prototyping headers for easy connection to the device's pins. cy3210-29x66 provides evaluation of the cy8c29x66 psoc device family. [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 32 of 34 device programmers all device programmers can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note : cy3207issp needs special software and is not compatible with psoc programmer. this software is free and can be downloaded from http://www.cypress.com . the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) third party tools several tools have been specially designed by the following 3rd-party vendors to accompany psoc devices during devel- opment and production. specific details for each of these tools can be found at http://www.cypress.com under design resources > evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, see application note ?debugging - build a psoc emulator into your board - an2323? at http://www.cypress.com . table 35. emulation and programming accessories part number pin package pod kit [19] foot kit [20] adapter [21] CY8C29466-24PVXA 28 ssop cy3250-29x66 cy3250 -28ssop-fk as-28-28-02ss-6enp-gang notes 19. pod kit contains an emulation pod, a flex-cable (co nnects the pod to the ice), two feet, and device samples. 20. foot kit includes surface mount feet that can be soldered to the target pcb. 21. programming adapter converts non-dip package to dip footprin t. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com . [+] feedback
cy8c29466 document number: 001-12899 rev. *b page 33 of 34 ordering information the following table lists the automotive cy8c29x66 psoc devices? key package features and ordering codes. ordering code definitions table 36. cy8c29x66 automotive psoc device key features and ordering information package ordering code flash (bytes) ram (bytes) temperature range digital psoc blocks analog psoc blocks digital i/o pins analog inputs analog outputs xres pin 28 pin (210 mil) ssop CY8C29466-24PVXA 32k 2k -40c to +85c 16 12 24 12 [1] 4 yes 28 pin (210 mil) ssop (tape and reel) CY8C29466-24PVXAt 32k 2k -40c to +85c 16 12 24 12 [1] 4 yes cy 8 c 29 xxx-spxx package type: thermal rating: px = pdip pb-free a = automotive -40 c to +85 c sx = soic pb-free c = commercial pvx = ssop pb-free e = automotive extended -40 c to +125 c lfx/lkx = qfn pb-free i = industrial ax = tqfp pb-free cpu speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress [+] feedback
document number: 001-12899 rev. *b revised september 25, 2009 page 34 of 34 psoc designer? is a trademark and psoc? is a registered trademark of cypress semiconductor corp. purchase of i2c components fro m cypress or one of its sublicensed associated companies conveys a license under the philips i2c patent rights to use th ese components in an i2c system, provided that the system confor ms to the i2c standard specification as defined by philips. all other products and company names mentioned in this document may be the trademarks of their respective holders. cy8c29466 ? cypress semiconductor corporation, 2007-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at www.cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document title: cy8c29466 automotive psoc ? programmable system-on-chip document number: 001-12899 rev. ecn no. orig. of change submission date description of change ** 772096 hmt see ecn new silicon, new document (revision **). *a 2697720 vivg/pyrs 04/24/09 updated template content edits *b 2769233 btk 09/25/09 updated features section. updated text of psoc functional overview section. updated getting started section. made corrections and minor text edits to pinouts section. changed the name of some sections for added clarity. improved formatting of the register tables. added clarifying comments to some electrical specifications. changed t ramp specification per masj input. fixed all ac specifications to conform to a 5% imo accuracy. made other miscella- neous minor text edits. deleted some non-applicable or redundant information. added a footnote to clarify that 8 of the 12 analog inputs are regular and the other 4 are direct sc block connections. updated the development tool selection section. improved the bookmark structure. edited f imo6 , t eraseb , t write , t rsclk , t fsclk , v ihp , v pporxr , and 5v reflo specifications according to masj input. removed ?tm? from programmable system-on-chip in the title. [+] feedback

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